Modern wireless communication networks, such as wideband code division multiple access (WCDMA) and long term evolution (LTE), make use of complex modulation schemes to maximize the data throughput in limited bandwidth. Their resultant communication signals are characterized by a high peak-to-average power ratio (PAPR). This put the emphasis on the importance of improving the average efficiency of RF power amplifiers when driven with high PAPR signals by reducing their power consumption in the back-off region. To obtain the high efficiency at a high back-off power state, numerous efficiency boosting techniques such as EER, ET, LINC, and Doherty have been proposed. Among these, the Doherty power amplifier (DPA) has experienced widespread acceptance and development in recent years, which has been reported to deliver considerably high efficiency because of its advanced design with a simple structure.
In a classical two-way Doherty amplifier shown in FIG. 1, two amplifiers are included: a carrier amplifier (CA) and a peaking amplifier (PA), and their power capability (ratio) is: CA:PA=1:n. The back-off point is at K=1/(1+n), in dB=10 log(k)2. The output powers of two amplifiers operating at a proper phase alignment and bias level are combined in parallel using a quarter-wave transmission line)(Zo1/90° without the use of any additional components. This “self-managing” characteristic of the Doherty amplifier has made its implementation attractive for various applications. The simplest Doherty amplifier operation can be achieved using two cells with a class-AB biased carrier amplifier cell and a class-C biased peaking amplifier cell, so that they operate at a different power region of an input signal. The carrier amplifier is operational at a low power region and the peaking amplifier is turned on at a high power region.
In the symmetrical two-way Doherty amplifier configuration with same power device for the carrier and peaking amplifier (n=1 in FIG. 1), the saturation power of the carrier amplifier is one-fourth of the maximum system output power. This results in an efficiency peak at 6-dB output power back-off from the normal peak efficiency power level. In the past few years, researchers have focused on the design of asymmetrical Doherty amplifiers (n>1) with uneven power splitter, where the saturation of the carrier amplifier is at a lower level compared to the classical design. Theoretically, asymmetrical Doherty amplifier designs exhibit a significant drop in efficiency in the region between the efficiency peaking points, with the extent of efficiency reduction being proportional to the back-off level, as shown in FIG. 2 illustrating theoretical efficiency characteristics of various DPAs.
Nevertheless, it is possible to use more than two amplifiers to maintain the efficiency without significant dropping throughout the back-off region and extend the back-off level far beyond the classical design. This is the so-called multi-stage or multi-way or N-way (N>2 is a natural number) Doherty amplifier. For instance, the existing two types of 3-way DPAs shown in FIG. 3(a) and FIG. 3(b) have a superior efficiency characteristic because they have three maximum efficiency points along the output power level with the power capability of CA:PA1:PA2=1:n:m. In FIG. 3(a), the first back-off point is at K1=(1+n)/(1+n+m); and the second back-off point is at K2=1/(1+n). In FIG. 3(b), the first back-off point is at K1=n/(n+m); and the second back-off point is at K2=1/(1+n+m).
FIG. 3(a) is a widely known structure as described in Srirattana et al. “Analysis and design of a high-efficiency multistage Doherty power amplifier for wireless communications”, IEEE Transactions on MTT, March 2005. The topology is a parallel combination of one DPA used as a carrier amplifier with an additional peaking amplifier. The first peaking amplifier (PA1) modulates the load of the carrier amplifier initially and the second peaking amplifier (PA2) modulates the load of the previous Doherty stage at a higher power. The topology in FIG. 3(b) has recently been reported by Gajadharsing et al., “3-way Doherty amplifier with minimum output network”, U.S. Pat. No. 8,022,760 B2, September 2011. This topology is a parallel combination of one carrier amplifier and one DPA used as a peaking amplifier. Both of the 3-way DPA architectures in FIGS. 3(a) and 3(b) use three power amplifier units, and the two peaking amplifiers are turned on sequentially. Thus, three peak efficiency points are formed respectively at the two turn-on points and at the peak power.
However, due to the lower bias point of the peaking amplifier, its current level is always lower than that of the carrier amplifier. The load impedances of both cells cannot be fully modulated to the value of the optimum impedance for a high power match. Thus, neither cell can generate its respective full power. This limited load modulation will influence the carrier and peaking amplifier working conditions with each other and is often reported as the main source of not only causing a decrease of the maximum output, but a deterioration of a high efficiency operation region. To solve this problem, a more advanced architecture for maximizing performance of a DPA is to utilize the mixed-signal techniques to establish baseband/digital input control of the individual amplifier cells. This approach facilitates the uncompromised control and independent optimization of each amplifier's input drive conditions for maximum efficiency. FIG. 4 shows an existing dual-input digitally driven two-way DPA configuration with adaptive amplitude and phase alignment.
Further, for the output modulation characteristics of a DPA, the full loading matching circuits of the carrier and peaking amplifiers at both low and high power levels should be always required to satisfy the optimum Doherty operation. FIG. 5 illustrates the equivalent-load networks for the 2-way DPA including a simplified equivalent circuit of the active devices. As shown, the output equivalent circuit of the active device can be represented as an ideal current source whose shunt termination has a complex impedance of R+jX. As well known, a microwave Doherty amplifier with a quarter wave transformer can only perform a genuine resistive output matching process. To achieve this, sections of transmission lines which are well-known as offset lines should be inserted in the load matching network, so as to obtain a full output matching for both real and imaginary parts while preserving a highly improved efficiency.
However, these existing solutions set forth above still have some problems.
In practice, it is difficult to obtain the maximum efficiencies of the ideal Doherty at the peak and back-off power levels simultaneously due to the non-ideality of the active devices. FIG. 6 illustrates the typical degraded efficiency performance of a 2-way DPA. Despite the existing technologies to optimize the DPA performance, the active load modulation principle accomplished by the self-managing carrier and peaking amplifiers should be always satisfied. In essence, this load modulation characteristic of DPA also limits its own performance. To achieve the optimized performance, the design considerations on the carrier and peaking amplifiers are different. As to the carrier amplifier, it should be optimized for the overall power range with proper impedance transformation and the cooperation with peaking amplifier. On the other hand, as to the peaking amplifier, its turn-on point and the performance at peak power region should be also carefully optimized simultaneously in accordance with the carrier amplifier working operation. This is to say, the design of carrier and peaking amplifiers should be optimized not only individually, but also as a whole. As a consequence, more often than not, compromises have to be made for the overall performance, as depicted in FIG. 6.
Moreover, when the 2-way DPA is extended to the multi-way realizations which have been proposed recently for advanced communication system with higher PAPR, it will be yet more difficult to optimize the multiple peak efficiency points at back-off power simultaneously. Besides, the Doherty output matching method with offset lines will be less effective in the existing multi-way DPA structures. Since in the existing multi-way DPA realizations, the carrier and/or the peaking amplifiers experience more than two steady impedance states (low- and high-impedance state) with complicated impedance inverting networks. Taken the two types of the 3-way DPAs for example as shown in FIGS. 3(a) and 3(b), respectively, as to the first peaking amplifier (PA1) in the first 3-way DPA, it will endure three steady impedance states for three peaking efficiency points from open circuit state to medium impedance state, and then to low impedance state for high power matching as the input power increases. However, the insertion of offset lines after the output matching networks of the carrier/peaking amplifiers is not sufficient to optimize its efficiency performance. This is because the lengths of offset lines can only be tuned for optimizing one of the impedance states by maintaining another matching state without being changed. Similarly, the CA and PA1 of the second 3-way DPA with three impedance states in FIG. 3 (b) meet similar contradiction. If the power-dependent nonlinearities of the active devices are taken into consideration, it will be even more difficult to optimize the 3-way DPA's performance.
Hence, an improved architecture of Doherty amplifiers with improved performance would be advantageous and desired.